1. Field of the Invention
The present invention relates to a semiconductor memory device having a high-speed reading mode, called a burst mode. In particular, the present invention relates to a semiconductor memory device capable of successively reading data in a burst mode operation while avoiding increase in the chip area.
2. Description of the Related Art
Due to the development of high-speed microprocessors (MPUs) in recent years, there have been increasing demands for semiconductor memory devices capable of high-speed access.
One answer to such demands has been to increase the speed of the usual random access method; another has been to develop semiconductor memory devices having a burst mode, which provides for very fast reading at the expense of some limitation on the access method.
A read operation in the burst mode is achieved by simultaneously selecting a plurality of memory cells in a memory cell array corresponding to a row address designated by input address signals, and rapidly switching the column address so as to sequentially output the data stored in the respective memory cells.
FIG. 5 shows an example of a conventional semiconductor memory 1000 having a burst mode. FIG. 6 is a circuit diagram showing a Y-decoder/selector 1023, precharge circuits 1024, and a burst mode selector 1032. FIG. 7 is a timing diagram illustrating a high-speed read operation in the burst mode.
Hereinafter, any reference to a "memory" will be directed to a "semiconductor memory" unless otherwise specified.
The memory 1000 shown in FIG. 5 receives address signals A0 to A19, among which A0 to A6 designated a column address, and A7 to A19 designate a row address.
The memory 1000 includes a memory cell array 1010 in which memory cells M0i0, M0i1, . . . etc. (hereinafter collectively referred to as "memory cells M") each for storing 1-bit data are arranged in a matrix. The memory 1000 also includes a row selector for selecting the memory cells M corresponding to a row address designated by A7 to A19.
The row selector includes an input buffer circuit 11 for receiving the row address designated by A7 to A19, a predecoder (A) circuit 1012 for receiving the output therefrom, and an X-decoder 1013 for selecting a row WLi (the word lines WLi in FIG. 6, where i is one of 0, 1, 2, . . . , and i) of the memory cell array 1010 in accordance with a predecode output from the predecoder (A) circuit 1012.
In addition, the memory 1000 includes a column selector for selecting a plurality of columns of memory cells respectively corresponding to a column address designated by A0 to A6. The column selector includes an input buffer circuit 1021 for receiving a column address designated by A3 to A6, a predecoder (B) circuit 1022 for receiving the output therefrom, a Y-decoder/selector 1023 for receiving predecode outputs CA0 to CA7, and CB0 to CB3 from the predecoder (B) circuit 1022, an input buffer circuit 1030 for receiving the address signals A0 to A2, a burst mode decoder circuit 1031 for receiving the output therefrom, and a burst mode selector 1032 for receiving the outputs BS0 to BS7 from the burst mode decoder 1031.
To the Y-decoder/selector 1023 is coupled the precharge circuits 1024 for precharging common bit lines CBIT0 to CBIT7 (hereinafter collectively referred to as "common bit lines CBIT") designated by the column addresses. The common bit lines CBIT are coupled to sense amplifiers (not shown) in a read circuit 1033. An output circuit 1020 is coupled to the read circuit 1033. The output circuit 1020 outputs the output Dout of the read circuit 1033 to an output terminal 2.
Next, the high-speed read operation of the memory. 1000 having the above structure in the burst mode will be described. First, the row address signals A7 to A19 are input to the predecoder (A) circuit 1012 via the input buffer circuit 1011 and decoded by the predecoder (A) circuit 1012 and the X-decoder 1013, so that one of the word lines WLi goes active (i.e., the "High" level) with the timing shown in FIG. 7.
The column address signals A3 to A6 are input to the input buffer circuit 1021, and the output thereof is decoded by the predecoder (B) circuit 1022, so that the predecode outputs CA0 to CA7 and CB0 to CB3 are applied to the Y-decoder/selector 1023. The Y-decoder/selector 1023 selectively couples to the respective common bit line each of the memory cells that are coupled to the word lines WLi. Then, the precharge circuits 1024 performs a precharge for each common bit line CBIT coupled to the respective memory cells for a predetermined period of time. After the precharge is completed, the potential of the common bit line CBIT is amplified by a sense amplifier in the read circuit 1033, and the output circuit 1020 causes the output Dout of the read circuit 1033 to be output to the output terminal 1002 with the timing illustrated in FIG. 7.
In the above-described conventional memory having a burst mode, a higher speed data reading can be achieved by precharging at a predetermined potential the common bit lines CBIT associated with a block to be read next. A conventional example of adopting this technique is disclosed, for example, in Japanese Laid-open Publication Nos. 61-271683 and 1-137491.
The structure and operation of such a memory will be described with reference to FIGS. 8 and 9. FIG. 8 is a block diagram showing the memory. FIG. 9 is a timing diagram illustrating the operation of the memory.
As shown in FIG. 8, the memory includes a write circuit 1020, a write address pointer 1021, a read circuit 1040, a read address pointer 1031, and memory cells MCmn.
Next, the operation of the memory will be described with reference to FIG. 9. As shown, the precharge signal PRC goes "High" prior to a read cycle RC0 for reading data from the memory cell MCmn, and all the bit lines RBL0 to RBL7 dedicated to reading are precharged at the "High" level.
Hereinafter, a bit line dedicated to reading, a word line dedicated to reading, etc. will be referred to "a read bit line", "a read word line", etc.
Next, after the rise of the read clock signal RCK, the precharge signal PRC goes "Low", and the precharging for all of the read bit lines RBL0 to RBL7 is completed.
Furthermore, in response to the precharge signal PRC going "Low", the signal on the selected read word lines RWLn rises. As a result, the data stored in the memory cell MCmn coupled to the selected read word lines RWLn carrying the signal which has risen is output to the read bit line RBLm. Then, one of the eight read bit lines RBL0 to RBL7 is selected by a read bit line selection signal REB (see FIG. 8), and the potential of the selected bit line RBLm is detected and amplified by a sense amplifier in a read circuit 1040 and thereafter output as data Dout.
Before the occurrence of the next read cycle RC1, the read word line RWLn is lowered to the "Low" level by a sense complete signal or the like. Thereafter, the precharge signal PRC is raised in order to read data from the memory cell MCm+1n coupled to the next read bit line RBLm+1, thereby beginning a precharge for all of the read bit lines RBL0 to RBL7.
Another conventional memory capable of yet higher-speed reading is disclosed in Japanese Laid-open Publication No. 8-63990 filed by the Applicant. In accordance with this memory, the sense amplifier section of the read circuit is multiple divided so as to enable successive reading of page data, thereby achieving high-speed reading without a time lag during page switching.
The structure and operation of this memory will be described with reference to FIGS. 10 to 12. FIG. 10 is a block diagram illustrating the structure of the memory. FIG. 11 is a specific circuit diagram thereof. FIG. 12 is a timing diagram illustrating the operation thereof. Since the circuit structure of this memory is similar to that of the memory shown in FIG. 5, the corresponding components are denoted by the same reference numerals as used in FIG. 5.
In this memory, the column selector includes an input buffer circuit 1021, a predecoder (B) circuit 1022, and a Y-decoder/selector 1123. As shown in FIG. 12, a plurality of rows in the memory cell array 1010 corresponding to the column addresses designated by the input address signals are selected along with a plurality of columns other than the relevant column addresses. As a result, 2 pages of page data including the page data corresponding to the column addresses designated by the input address signals can be simultaneously read into a sense amplifier section (sense amplifier (0) circuits 1224a, and sense amplifier (1) circuits 1224b).
Accordingly, at time t5, where the reading of the page data of the address designated by the input address signals is complete and the reading of the page data of the next address begins, the page data of the next address has advantageously been read into the sense amplifier section.
Therefore, in accordance with this memory, the high-speed reading operation from the sense amplifier is not disrupted by the page switching for successively reading the page data. As a result, a continuous high-speed read can be realized.
However, in accordance with the conventional memory having a burst mode disclosed in Japanese Laid-open Publication Nos. 61-271683 and 1-137491, all of the selected common bit lines CBIT are precharged, thereby resulting in relatively high power consumption.
In addition, the recent trend in response to the gradual increase in memory capacity has been to increase the capacitance of the common bit lines CBIT (which need to be precharged as mentioned above). Therefore, the precharge time required for precharging the common bit lines CBIT has become long relative to the sensing time required by the sense amplifiers. The increased precharge time for the common bit lines CBIT inevitably results in a long cycle time required for one read cycle, which has presented certain constraints to increasing the read speed of such memories.
The memory having a burst mode disclosed Japanese Laid-open Publication No. 8-63990 requires at least twice as many sense amplifiers as the number of pages of data. Since all of the sense amplifiers are operating during a burst mode operation, relatively high power is consumed. Moreover, such a large number of sense amplifiers leads to an increased chip size.
The above problems will be described in more detail with reference to FIGS. 11 and 13. In this memory, as shown in FIG. 11, eight common bit lines CBIT (CBITA0 to CBITA3, CBITB0 to CBITB3) are always precharged at the time of random access and the first access in a burst mode. In the second and subsequent accesses in the burst mode, too, the eight common bit lines CBIT are always precharged.
The precharging function is performed by the precharge transistors (p-channel MOS transistors) 1050 shown in FIGS. 11 and 13. Firstly, since it is impossible to employ transistors having high driving ability for the precharge transistors 1050, the precharge time is inevitably prolonged.
Secondly, high power is consumed because the eight common bit lines CBIT are always precharged at Vcc.
Thirdly, since a sense amplifier SA is required for every common bit line CBIT, the total area occupied by the sense amplifiers SA per unit chip area becomes large, resulting in an increase in the chip size.
Fourthly, such large sense amplifier area in itself increases power consumption.